Miniaturization of integrated circuits is increasing the probability of frequent resistive open defects, which cause delay faults (malfunctions of circuits caused by signal delay), in circuits. Since a resistive open defect, unlike a full open defect, does not prevent a signal from flowing through the circuit, the impact of a resistive open defect on the behavior of the circuit that is seemingly properly operating at the factory may become noticeable in use after the shipment of the circuit. Therefore resistive open defects need to be adequately eliminated prior to shipment of circuits.
Logic testing using an automatic test pattern generation tool such as an automatic test pattern generator (ATPG) is being commonly used for testing integrated circuits. Techniques relating to circuit testing are disclosed in Japanese Laid-Open Patent Publication Nos. 2007-139603 and 2007-263790, for example.
However, while the logic testing using ATPG is effective for detection of stuck-at faults in which a logical value input into or output from a particular element is stuck at 0 or 1, the logic testing is not useful for detecting delay faults. This is because the ATPG generates test patterns from function-level circuit information and therefore does not assume delay faults at all.